The present invention relates to a decoder in a radio paging receiver and, more particularly, to a preamble detector which can detect a preamble in a radio paging signal within a short period of time.
A conventional radio paging receiver comprises a receiving section 201, a decoder section 202, and an alert generator 203, as shown in FIG. 2. The receiving section 201 is intermittently operated in response to a battery saving control signal CONT to reduce power consumption. The decoder section 202 processes received data DATA demodulated by the receiving section 201. When the decoder section 202 detects an address of its own receiver from the received data DATA, it outputs an address detection pulse ADET. The alert generator 203 performs an alert operation using a speaker, an LED, and the like in response to the address detection pulse ADET.
The format of a paging signal consists of a preamble (PA) comprising a repetitive pattern of "1" and "0" signals, and a plurality of batches which follow the preamble, as shown in FIG. 6, as recommended in, e.g, the CCIR (CCIR RPC No. 1, also called a POCSAG code). One batch includes one synchronization signal (SC) and eight frames. An address signal is sent as a codeword in a predetermined frame.
In order to receive the paging signal described above, the decoder section 202 (FIG. 2) comprises a bit synchronization circuit 301, a preamble detector 302, a synchronization signal detector 303, an address detector 304, and a reception controller 305, as shown in FIG. 3.
The conventional preamble detector comprises a shift register consisting of D flip-flops 401 to 404, and an AND gate 406, as shown in FIG. 4. More specifically, the preamble detector samples the received data DATA in one phase of a clock CLK extracted by the bit synchronization circuit 301 (FIG. 3) to perform a preamble detection operation.
The operation of the decoder section 202 (FIG. 2) of the conventional paging receiver will be described below. The operation of the decoder section can be classified into three states, i.e., a preamble search mode, a synchronization signal search mode, and an address search mode.
Referring to FIG. 5A, in the preamble (PA) search mode, the receiving section is cyclically turned on (CONT="1"). At this time, the bit synchronization circuit 301 and the preamble detector 302 shown in FIG. 3 are enabled (enable signal BENA=enable signal PAENA="1"). The bit synchronization circuit 301 corrects the phase of a clock to be synchronous with the received signal. The preamble detector 302 samples the received data DATA in response to the clock CLK output from the bit synchronization circuit 301, and checks the presence/absence of the preamble PA.
When the preamble PA is detected (preamble detection pulse PADET="1"), the decoder section 202 (FIG. 2) enters the synchronization signal (SC) search mode. At this time, the reception controller 305 causes the receiving section 201 (FIG. 2) to continuously operate, and enables the synchronization signal detector 303 (enable signal SCENA="1"). When the synchronization signal detector 303 detects the synchronization signal (synchronization signal detection pulse SCDET="1"), frame synchronization is established, and the decoder section 202 enters the address search mode.
In the address search mode, the reception controller 305 causes the receiving section 201 to intermittently operate at timings of frames assigned to its own receiver, and enables the address detector 304 (enable signal AENA="1"). The bit synchronization circuit 301 is enabled when the receiving section 201 is set ON even in the address search mode so as not to miss bit synchronization during long data. In this case, a time constant for clock phase correction is normally set to be large so as to prevent clock phase disturbance caused by noise (BMODE="0") When the address detector 304 detects an address assigned to the receiver, it outputs an address detection pulse (ADET="1"). In response to the address detection pulse, the alert generator 203 (FIG. 2) is enabled, to make the speaker, the LED, and the like operate, thus alerting the user to detection of paging.
When the synchronization signal cannot be detected from a predetermined number of (e.g., two) consecutive paging signals, or when an address code error is detected from consecutive paging signals, it is determined that frame synchronization is missed. Thus, the decoder section is restored to the preamble (PA) search mode. When the preamble is detected, it is also determined that frame synchronization is missed, and the decoder section is restored to the synchronization signal (SC) search mode (U.S. Pat. No. 4,839,639).
In the decoder section of the conventional radio paging receiver, the preamble detector 302 checks the preamble PA in only one phase of the clock output from the bit synchronization circuit 301. Therefore, in the preamble search mode, the decoder section first performs a bit synchronizing operation, and detects a preamble after bit synchronization is established. Therefore, it takes much time until the preamble is detected. In other words, when the receiving section is intermittently operated, the ON time of the receiver (T.sub.BS in FIG. 5A) must be increased by a time period necessary for bit synchronization, resulting in poor battery saving efficiency.
As shown in FIG. 5A, when data bursts are consecutively supplied at short intervals (T.sub.1 &lt;&lt;batch length in FIG. 5A), the two bursts normally have different bit phases. For this reason, the conventional preamble detector shown in FIG. 4 may fail to receive the preamble of the second data burst when the duty ratio of the preamble is offset from 50% due to an offset of characteristics of the receiving section, as shown in FIG. 7A. In this case, an address (A.sub.3) included in the second burst shown in FIG. 5A cannot often be received.